1. Technical Field
The disclosure herein relates to a data relay apparatus and a semiconductor integrated circuit having the same, and in particular, to a data relay apparatus that relays data according to clock timing of a receiver and a transmitter, and a semiconductor integrated circuit having the same.
2. Related Art
A conventional semiconductor integrated circuit includes a receiver and a transmitter to perform a data transmission/reception operation. The semiconductor integrated circuit is demanded to continuously perform a high-speed operation. Accordingly, in a recent semiconductor integrated circuit, each circuit region includes a PLL (Phase Locked Loop) circuit, and generates a clock that synchronizes with timing of input data. The receiver and the transmitter operate on the basis of clocks, which are generated from each of the PLL circuit, respectively. The clocks are generated in different forms according to data input timing.
As such, if the clocks of the receiver and the transmitter have different toggle timing, data that is transmitted from the receiver to the transmitter is rarely accurately transmitted due to a phase difference between the clocks, and accordingly stability in using the receiver and the transmitter is deteriorated. In order to prevent the stability of the data transmission/reception operation from being deteriorated, it is necessary to relay data in consideration of the phase difference between the clock of the receiver and the clock of the transmitter. However, the known semiconductor integrated circuit does not perform the data relay operation in consideration of the phase difference between the clocks. As a result, there is a limitation in implementing a high-speed semiconductor integrated circuit.